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Name Size Revision Age Author Comment
  branches 1 480 days Oleksiy Lukin initial xSoC release
  tags 1 480 days Oleksiy Lukin initial xSoC release
  trunk 33 190 days Andrey Popelo openrisc_bram.pl utility improved and some mino...

Latest revisions

# Date Author Comment
33 01/21/2010 12:08 AM Andrey Popelo

openrisc_bram.pl utility improved and some minor updates in Makefiles.
32 01/12/2010 03:02 PM Andrey Popelo

Live streams test for memory controller model added.
31 01/12/2010 03:00 PM Andrey Popelo

Some minor enchanstments in memory controller model
30 12/23/2009 06:25 PM Andrey Popelo

Added a document 'Implementing DDR2-400 Memory Interfaces in Spartan-3A FPGAs' for Spartan 3A DSP board.
29 12/22/2009 11:51 AM Andrey Popelo

Some minor changes in Memory controller simulation model.
28 12/21/2009 10:38 PM Andrey Popelo

Simple memory controller simulation model created using Python and SimPy library.
27 12/14/2009 04:07 PM Andrey Popelo

Replaced 'Spartan 3A' Family data sheet with 'Spartan 3A DSP' Family data sheet.
26 12/09/2009 07:43 PM Andrey Popelo

ddr2mig_to_wb module changes: debug pins added, documentation added, synthesizable testbench added.
25 12/08/2009 12:56 PM Andrey Popelo

Replaced ucf file for ddr2mig_to_wb testbench.
24 12/07/2009 10:32 PM Andrey Popelo

More comments for ddr2mig_to_wb module added.

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